Arasan Chip Systems has announced the MIPI LLI (low-latency interface) controller IP along with a matching type-1 M-PHY. The LLI is a chip-to-chip link layer interconnect protocol that allows low-latency cache refills from the DRAM associated with a companion chip. This removes the need for two separate sets of DRAMs, claims the company. A combined…
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Low Latency Interface Controller IP Has Type-1 Physical Layer for Host Buses
July 11th, 2012
MIPI® Alliance Drives Advancements in Mobile Device High Speed / Low Power Data Transport Protocol Technology with Interoperability Event
June 28th, 2012
Piscataway, NJ, June 26, 2012 – MIPI Alliance today announced a successful interoperability event, featuring the near-final UniProSM v1.41 specification. Hosted by Agilent Technologies, Inc., the event enabled Arasan Chip Systems, Inc., Samsung Electronics Co., and Toshiba Corporation to test interoperability, using a Test-M-PHY (T-MPI) interface. The main functions of UniPro (Link Startup, Power Mode…
MIPI Alliance Highlights Member Demos and New Specifications at Mobile Asia Expo
June 20th, 2012
MIPI Alliance will host 6 member companies in its booth at the 2012 Mobile Asia Expo, June 20-22 in Shanghai, China. In addition, the industry-leading mobile interface standards organization will announce two updated specifications – the optimized physical layer M-PHY v2.0 with high bandwidth capabilities, and the UniPro v1.41 unified, layered protocol stack which builds…
ChipEstimate.com Has the Largest Selection of Semiconductor Bus Interface IP from Leading IP Vendors
June 20th, 2012
San Jose, California, United States of America (Free-Press-Release.com) June 19, 2012 – June 19, 2012 – The semiconductor IP catalog on ChipEstimate.com has over 9,000 semiconductor IP components from the EDA industry’s leading IP vendors, including more than 400 Bus Interface IP cores. The specific types of Bus Interface IP components include AGP IP, CAN…
EDA Cafe´ Interviews Andrew Haines, VP of Marketing, at DAC 2012
June 12th, 2012
Interview with Andrew Haines at DAC 2012
EDACafe Interviews Andy Haines at DesignCon 2012
February 9th, 2012
Click to view on EDACAfe.com “IP Solutions Update: UFS Hardware Verification Platform, MIPI, and Analog PHY”, Andrew Haines, Vice President Marketing, Arasan Chip Systems
Are jobs coming back to the US – video interview
February 3rd, 2012
Andy Haines, VP of Marketing for Arasan Chip Systems, on the floor of Design Con Feb 1, 2012. Video Link
Full-Speed Hardware Validation Platform Now Mimics High-Speed Serial Analog Interfaces
January 19th, 2012
CHIP DESIGN Magazine – By Dave Bursky, Technology Editor. The third generation of Arasan Chip Systems’ Hardware Validation Platform (HVP) adds the ability to perform early validation of a new interface by emulating the complementary device at the interface protocol level. Read the full article
Why MIPI is going to revolutionize the way you design
August 23rd, 2011
Why MIPI is going to revolutionize the way you designAn article by Prakash Kamath, VP of Engineering, Arasan Chip Systems
