Arasan Chip System offers  a challenging and rewarding work environment in delivering  leading edge technology for the Mobile industry. As part of the expanding growth in this segment ACS is looking for a senior ASIC digital design engineer.

The candidate will have the opportunity to develop IP cores used in Mobile storage and Mobile connectivity.

Candidate must have a BSEE with 7 to 10 yrs  or MSEE with 5 to 10 years ASIC design and verification experience. Candidate must be motivated, results oriented with a proven track record  in one or more of these areas:

• Protocol expertise in an interconnect standards such as  MIPI, USB, PCIE, JEDEC.
• Protocol expertise in system bus standards such as AXI/AHB.
• Developing System Architecture and/or module  level Microarchitecture specifications.
• Hands-on experience with Verilog RTL coding and debug.
• Problem solving and analytical skills.
• FPGA prototype  debug and system bring up skills; expertise with debug equipment such as analyzers and scopes.
• Good written and spoken communication skills and technical documentation skills.
• Technical leadership and project management skills.

Send Application to DesignJobs@nullarasan.com

Job Site: San Jose, CA 

Job Description: Design Manager for physical interconnects such as DPHY, MPHY, UHS-II, ONFI and HSIC. Key responsibilities include: 1) Project planning, schedules, resource allocation, personnel development, and employee reviews; 2) Drive requirements discussions, technical issues and other design aspects with internal teams and with customers from inception to product ramp; 3) Develop process driven methodologies for customer collaterals and project documents with a goal towards ISO standard certification; 4) Technical management of the AMS team for PHY – Architecture, Analog Design, RTL, DFT and Back-End sign-off; 5) Supervise the process of “Netlist to GDS-II” flow including Static timing analysis and Physical Design (Place and Route); 6) Resolve Integrated Circuits problems in the laboratory; and 7) Lead the development of innovative software methodologies to bring in automation in design and verification of analog circuits. Travel Required.

Special Requirements:  Deep understanding of deep sub-micron technologies (e.g., 90nm, 45/40nm and 32/28nm).  Ability to lead a team with knowledge of project tracking systems.  Knowledge of processes and process-driven project management.  Ability to identify and clearly articulate issues and solutions at various stages of the project.  Ability to understand system requirements and translate it into module-level specifications.  In-depth knowledge of IC design involving mixed signal circuits.  Extensive understanding of architecture of various systems including ability to do hands-on design of circuits such as PLL, CDR and PnR of digital blocks.

Minimum Requirements: Master’s in Electrical Engineering and 2 years of related experience.

Mail resume to: Arasan Chip Systems, Attn: HR, Job Code DM-SS, 2010 N. First Street, Suite 510, San Jose, CA 95131.

Job Description

• Development of high speed SERDES for MIPI, D-PHY and M-PHY applications, with an extension to other projects such as; USHII, USB 2.0 and USB 3.0.
• Architecture definition, schematic generation, layout generation, blocks assembly, verification, and lab evaluation.
• Provide technical interface to customers, milestone and deliveries.
• Responsible for technical leadership and mentoring of junior design engineers.
• Will be required to seek and encourage new approaches and architectures for Market advantage.
• Ensure on time delivery and quality of PHY IP and active involvement in problem solving & implementing opportunities for improvement.
• Interfacing / interacting with other development teams.

View the full job description here.

Send Application to Analogjobs@nullarasan.com

Job Description:

• 6- 10+ years design experience in CMOS Analog / Mixed Signal Circuit Design using advance digital process technology.
• Experience in at least one of these high speed interfaces USB2.0, USB3.0, D-PHY, M-PHYI, M-PHYII, USHII, PCI express, SATA etc
• Strong fundamental understanding of transistor devices and analog transistor level design
• Hands on design experienced in high speed low jitter PLL, DLL , transmitters, receivers, equalization, oscillator, biasing circuits, bandgap references, regulators, op-amps and high speed clocking circuits.
• Experience in usage of IC design tools like Cadence / Mentor for Analog Circuit Design, Circuit Simulation, System Simulation, and Layout design, Physical Design, Physical Verification, Parasitic Extraction and Full Chip Verification.
• Scripting Skills (Perl) as well as modeling and design skills in Verilog/Verilog AMS
• Will be required to work independently with limited supervision and be a team player

View the full job description here.

Send Application to Analogjobs@nullarasan.com

Download the full job descriptionhere

Send Application to Marketingjobs@nullarasan.com

The Product Marketing Manager – Mobile Connectivity is the company’s primary business interface with global standards bodies that create Mobile Connectivity standards. The main focus is on MIPI. Arasan Chip Systems is the leading provider of MIPI interface IP including Camera, Display, SLIMbus, High-Speed Interface, D-PHY and M-MPHY IP. The Product Marketing Manager is responsible for representing the company’s viewpoint within the relevant standards bodies and communicating developments within the standards process that impact business or future business back to the company. The Product Marketing manager will be interfacing with customers and sales to communicate the features and benefits of the company’s products. The product marketing manager is responsible for the key messaging and positioning for his products and insuring that these messages are widely disseminated in the customer community.

View the full job descriptionhere

Send Application to Marketingjobs@nullarasan.com

LOCATION – Santa Clara, CA

EVENT DATE - May 1-2, 2013

Yuping Chung, Product Markting Manager at Arasan, will present:

“Design Considerations of eMMC & UFS Controllers”

 1.       Understand the technical detail of UFS and eMMC physical interface

 2.       Understand the importance of compliance and interoperability of eMMC and UFS

 3.       Understand the right IP and tools for designing robust UFS and eMMC controllers

San Jose, California – April 18, 2013 - Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions for mobile applications, announced today the availability of the industry’s first SD 4.1 Total IP Solution for engineering and product development of SD 4.1 devices with the UHS-II physical layer interface.  Arasan is an active contributor to SDA specification.  Based on its in depth involvement and knowledge of the new specification, and its field proven SD 4.0 IP, Arasan is making this new SD 4.1 total IP solution available to customers who are the leaders, providing the most advanced feature set in the mobile applications.

To meet the ever increasing data transfer rate in high end applications, such as professional broadcasting transmission or advanced high resolution display, the SD 4.1 specification calls out the maximum performance of 1.56 Gbps at UHS-II full duplex mode per lane or half duplex UHS-II at 3.16 Gbps.  In real applications, due to the system overhead and different SD 4.1 device controller designs, the actual measured performance can vary dramatically from system to system.  With the newly introduced ADMA 3, the OS driver is now able to issue multiple read or multiple write commands at once, without having to wait for the SD controller to complete one command at a time.  Once the SD host controller has collected multiple commands, it will then manage and complete them without intervention from the host software drive.  Thus, the UHS-II 1.56 Gbps interface can be more effectively utilized and maximize the system throughput.  This feature can be very useful when running multithreaded applications where multiple applications are constantly updating their status or swapping their contents by writing or reading small chunk of data to or from the memory card.

Helping engineers to accelerate time to market, Arasan provides a complete suite of tools for IP integration including SD 4.1 link layer controller IP, UHS-II PHY in advanced process technologies, verification IP with robust test suite, FGPA validation and development platform, and software stack in source code.  The link layer controller IP is designed with the most interoperability in place, based on Arasan’s extensive experience in working with many SD host and SD device companies.   Arasan has conducted several interoperability tests to ensure wide range of compatibility with different products in the market.  Developed in advanced, 40nm and below process nodes, the UHS-II PHY is designed for higher signal integrity and lower power consumption compared to competition. Arasan has optimized it Linux based SD software driver and tested its performance by running the Linux storage device benchmark; the benchmark results demonstrated the software driver achieving more than 90% bandwidth efficiency to squeeze out every bit of performance improvement.

Incorporating Arasan’s SD 4.1 IP on a FPGA board with the software stack on a Linux based system, Arasan provides a Hardware Validation Platform (HVP) which enables early validation of SD 4.1 specification by emulating the SD 4.1 Host at the interface protocol level. Beyond this, it facilitates early application development for reference board designs and production testing, before the SD 4.1 memory cards are available in silicon. Further in the product cycle, the HVP acts as a reference platform to help identify any incompatibilities between the device under development, and the silicon device it is communicating with.

Availability

Arasan is engaging with customers now on the SD 4.1 Total IP Solution, including SD 4.1 Controller IP, UHS-II, Verification IP (VIP), Linux Software Stack in source code, Hardware Validation Platform (HVP), and all supporting documents.

 About Arasan            

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications.   Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for MIPI, USB, UFS, SD, SDIO, MMC/eMMC, UFS, and many other popular standards.  Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.

Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services.   Based in San Jose, CA, USA, Arasan Chip Systems has a 17 year track record of IP and IP standards development leadership.

San Jose, California – April 16, 2013 - Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions for mobile applications, announced today its Support Everywhere! program providing in-depth technical support for its customers, regardless of their location, with the goal of providing the quickest possible solutions.    The reality of today’s SoC design teams is that they are dispersed across many time zones and locations.  Any one location may have purchased an IP, but many will be using it.  In order to provide the best possible support for today’s challenging development environment, Arasan has structured its customer support capability to provide the best in-depth support, in the shortest time, wherever the customer’s location.

Arasan’s unique approach to support employs IP developers in the front lines of customer support in order to bring customers into contact with the most knowledgeable engineer immediately.   Arasan’s customers are thus assured quick, effective support responses, cutting out middlemen, translation time and wheel spinning.   Located in San Jose, CA and India, the Arasan team is ready to provide support on a 24-7 basis.

First-hand knowledge of the IP is a necessary condition for first class support, but this must also be coupled with understanding of the latest developments in each relevant interface specification.   Arasan contributes to the development of many specifications through direct participation in standards bodies activities including JEDEC, UFSA, SD Association, the MIPI® Alliance and USB-IF.   Knowledge gained through current specification development activity is further enhanced by leadership positions in the SD/eMMC, UFS, MIPI Alliance and USB IP markets which bring Arasan engineering teams into broad contact with developments in the field, and has resulted in deep experience in applying these interface standards in a wide variety of situations.

Availability

Arasan is offering Support Everywhere!  immediately to all current and future customers as part of its annual support and maintenance programs.

About Arasan            

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications.   Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for MIPI, USB, UFS, SD, SDIO, MMC/eMMC, UFS, and many other popular standards.  Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.

Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services.   Based in San Jose, CA, USA, Arasan Chip Systems has a 17 year track record of IP and IP standards development leadership.