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10/100 Ethernet MAC IP core

The Arasan 10/100 Ethernet Media Access Controller (MAC) IP core is compliant with the Ethernet IEEE 802.3-2002 standard and has passed inter-operability testing at UNH-IOL. The 10/100 Ethernet IP core provides an 10/100 Mbps Media Independent Interface (MII) and an optional processor interface; it also supports Reduced MII (RMII) and Serial MII (SMII). The 10/100 Ethernet MAC IP is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers, and Ethernet adapter cards. The 10/100 Ethernet IP supports half-duplex mode at 10/100 Mbps and full-duplex mode at 10/100 Mbps.

The IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. An available 32-bit scatter-gather DMA transfer packets between the internal FIFOs and the host memory to enhance system performance. The IP core supports 4-bit MII based 10/100 Mbps PHY. IA MDIO/MDC (Management Data Input/Output and Management Data Clock) management interface provides controlling and management functions to external PHY devices.

The 10/100 Ethernet MAC IP provides enhanced programmable features for minimizing applications complexity and pre/post message processing. These features support MIB, SNMP, RMON, VLAN Q-Tag frame, and Jumbo frames. It also includes dynamic generation, checking, and stripping of FCS field, automatic pad field insertion, automatic re-transmission and detection of collision frames, collision avoidance and handling. Other features are generation and decoding of PAUSE control frames, frame boundary delimitation, frame synchronization, and error detection.

Diagram

10/100 Ethernet MAC IP Block Diagram, Fast Ethernet MAC IP core

Features

  • Full-duplex and half-duplex modes of operation
  • Supports IEEE 802.3-2008 compliant MII
  • Optional support for RMII, and SMII to reduce pin counts
  • Independent 32-bit scatter-gather DMA with big/ little endian operation
  • Optional VLAN Q-Tag frame support
  • CSMA/CD Protocol for half-duplex mode
  • PAUSE frame based flow control in full-duplex mode
  • MDIO/MDC management interface
  • 802.3 compliant MIB, SNMP, RMON management support
  • Configurable transmit and receive FIFOs
  • Supports Jumbo frames
  • Support magic packet and Wake-Up frames
  • Optional AXI, AHB, PCIe, PCI, or custom bus interface

Deliverables

  • RMM Compliant Synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents

Benefits

  • Fully compliant core
  • Premier direct support from Arasan IP core designers
  • Easy-to-use industry standard test environment
  • Un-encrypted source code allows easy implementation
  • Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured