SLIMbus Host

SLIMbus Host IP Core

The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose connectivity with multiple audio and other low/mid bandwidth peripheral devices. The Arasan SLIMbus Host Controller IP is designed to provide MIPI SLIMbus 2.0 compliant connectivity to a SoC.

As a SLIMbus Host, this IP is responsible for the establishment, maintenance and shutdown of the entire SLIMbus system under control of the host software drivers/stack and in response to the presence and bandwidth requirements of the various SLIMbus devices on the bus.

SLIMbus has a TDM channel allocation structure for control messages and data. When its Framer is active, the host drives the SLIMbus clock, creates the SLIMbus frames, and enables the various devices to synchronize and share the available bandwidth.

SLIMbus Host IP Core contains a configurable generic device that transfers data to and from remote SLIMbus components and the SOC’s system memory. Alternately, one or more port pairs of the generic device can be used by SLIMbus Host component to incorporate bridge functions to legacy interfaces, like I2S, I2C and SPI, or interface directly to audio DAC’s and ADC’s.

Diagram


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