CSI-3 Receiver IP Core
The Arasan CSI-3 Receiver IP is designed to provide MIPI CSI-3 compliant high speed serial connectivity for applications processors to corresponding camera modules in mobile platforms. Serial connectivity between this IP and an external the camera module’s CSI-3 transmitter is implemented using 1 to 4 M-PHY Receive lanes, depending on camera sensor resolutions and the resulting bandwidth needs. All configuration and status exchange with the camera module is done through a single M-PHY transmit lane. This IP connects to the M-PHY’s through the RMMI interface. On the Host side, the CSI-3 Receiver IP connects to the AHB, AXI or OCP bus through a slave interface for configuration by a device driver, using programmed IO. Pixel data is transferred directly between the Host Data Plane in the Camera Abstraction Layer (CAL) of the IP and an external ISP.
Diagram
Features
- Compliant with the MIPI specification CSI-3 Ver 1.0
- Configurable for up to 4 Receive lanes, with 1 Transmit lane
- Supports Type I M-PHY HS Gears 1 and 2
- Receives CSI-3 packets and converts to pixel stream
- Simple interface to Image Signal Processor (ISP)
- Choice of AHB/AXI/OCP interfaces to configure and control the CSI-3 receiver system
- Utilizes Unipro 1.41 for layers 1.5 (PHY Adapter) to 4 (Transport)
- Two layers of abstraction over the UNIPRO (TAL and CAL)
- Interleaving supported for multiple image streams each using different Cport number
- Standard pixel interface provided at the CAL layer
- Support for YUV, RGB, RAW, and compressed format
- Additional support for JPEG Type I, II, and III formats
Benefits
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
- Functionality ensured with comprehensive verification
- Premier direct support from Arasan IP core designers
Deliverables
- Verilog HDL of the IP Core
- Synthesis scripts
- Verification environment
- User guides for design and verification
