CSI-2 Receiver IP Core
The Arasan CSI-2 Receiver IP Core is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for applications processors to corresponding camera modules in mobile platforms. Serial connectivity between this IP and an external the camera module’s CSI transmitter is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY’s through the PPI interface.
Initial configuration of CSI2 Receiver IP and its associated Arasan D-PHY can be done through programmed IO over an AHB bus, however, other bus interfaces like AXI and OCP can be provided upon request.
This IP performs the data lane merging of image data received on PPI interface from D-PHY. It performs CRC and ECC checks to ensure the integrity of packet payload and header. Based on the user register settings, the IP either forwards or drops the erroneous packets. All forwarded packet payloads are then converted from byte to pixel format, decompressed and output to an external Image Signal Processor (ISP) of the applications processor’s graphics sub-system. All D-PHY Level errors, Packet Level errors and Protocol Decoding Level errors are communicated to the host from a status register.
Diagram
Features
- Compliant with the following MIPI specifications:
- Camera Serial Interface (CSI-2) version 1.01
- D-PHY version 1.1
- CSI-2 interface on camera facing side supports
- Connectivity to D-PHY through PHY Protocol Interface (PPI) Interface
- One to four data lane support
- Hi-Speed (HS) receive rates of 80 Mbps to 1.5Gbps per lane
- Low Power (LP) data transfer at 10 Mbps
- Continuous and stoppable clocks on clock lane
- Switching to and from Low Power (LP) and Ultra-Low Power (ULPS) modes
- AHB interface for register configuration and monitoring using programmed IO
- IP core and external ISP interface support
- All data formats specified in CSI-2 spec
- All packet level errors, and protocol decoding errors
- Synchronization failure detection and recovery
- Up to 4 image streams using virtual channels
- One pixel or two pixels per clock transfer to external image signal processor
Benefits
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
- Functionality ensured with comprehensive verification
- Product quality proven with silicon
- Premier direct support from Arasan IP core designers
Deliverables
- Verilog HDL of the IP Core
- Synthesis scripts
- Verification environment
- User guides for design and verification
