UniPro℠ Controller IP Core
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open standards for interfaces to mobile application processors. The Unified Protocol (UniPro) is one in a family of standards addressing the mobile market.
The Arasan UniPro Controller IP core is fully compliant with the UniPro specification version 1.4 and supports the physical adapter layer of the M-PHY® specification version 1.0. MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications. Designed to support up to 5Gbps per data lane, it is scalable from one to four bidirectional lanes. To achieve optimal performance the Arasan UniPro Controller implements the following layers in hardware: a) physical adapter layer, b) data link layer, c) network layer, and d) transport layer. TC0 and TC1 traffic classes are handled on a priority-based transmission, and additional features include support of multiple power modes, error detection and handling, and data transmission preemption.
Unique to the Arasan controller is optional support that utilizes end-to-end flow control within UniPro to maximize transmission throughput and efficiency.
Designed specifically for applications such as mobile phones, portable handheld media players, and mobile terminals, UniPro provides the high-speed connectivity needed between the applications processor and application devices such as wireless modules, graphics processors, multimedia accelerators, and storage subsystems. Targeted specifically for mobile phones, UniPro will be the high-speed chip connection of choice moving forward.
- MIPI UniPro Compliant
- Type I for M-PHY
- MIPI M-PHY Version 1.0
- Multi-lane: one to four
- Up to 5Gbps per lane for 4.0Gpbs maximum throughput
- Package base protocol
- Device Independent
- Priority-based traffic classes (TC0 & TC1)
- Preemption support during data frame transmission
- Autonomous error detection and handling
- Multiple power modes
- PHY Adapter (L1.5)
- Data Link (L2)
- Network Layer (L3)
- Transport Layer (L4)
- Fully compliant core with proven silicon
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Customer training available
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglas
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents