xD Host Controller IP
As the mobile industry continues to grow, the requirements for both internal and external memory are increasing at an exponential rate. At the system level, memory interfaces with larger capacities, smaller form factor and faster access times in addition to support for multiple industry standards are needed.
Arasan Chip System’s xD Host Controller IP is a highly integrated solution that is compliant with the xD Picture Host Guideline v1.2 and Card v1.2 specification. The controller handles all of the command, address and data sequences to manage the xD protocol. In addition it performs ECC generation and checking for xD. A host can access and configure this IP using the standard AHB bus interface. The host controller access data in the xD card using simple register accesses as the controller takes care of the timing and ECC specified by xD standard.
In addition to providing the xD Controller IP core, Arasan provides a complete verification and test environment as well as bus functional models to ease integration of this IP into an SoC.
Diagram
Features
- Compliance: xD Picture Card Host Guideline v1.2, xD Picture Card Specification v1.2
- Async: 8 bit data mode
- I/O: 8 bit data mode
- Supports all variants standard – Type M, M+, H
- Up to 2 GB capacity
- Comfortable erase mechanism
- Supports Master Mode operation
- Programmable Access Timing
- Supports Slave DMA Page Read, Write operations
- Supports ECC generation and checking
- Multi-block programming and Multi-block erase
Benefits
- Fully compliant core with proven silicon
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Customer training available
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
Deliverables
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
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