NAND Flash Controller IP Core
NAND Flash is being incorporated into many types of products requiring storage large capacity including portable memory drives, media players, digital cameras, PDAs, digital TVs, digital camcorders and PCs.
The Arasan NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable memory device up to 128 Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, and others. The IP core includes a host of configuration options from page size to band selects. The controller offers Hamming Code (1bit error correction and 2bit error detection) and BCH (option for 4-, 8-, 12-, up to 32 bit error correction) error code correction (ECC) for optimized performance and reliability. Additional features include the capability to boot from flash.
The IP core supports a variety of host bus interfaces for easy adoption into any design architecture – AHB, APB, OCP, 8051, or custom buses. The slave AHB IP supports an external DMA interface where the master AHB incorporates an internal DMA controller.
Diagram
Features
- Supports SLC and MLC devices
- Supports memories up to 128Gb
- Supports major vendors: Micron, Samsung, Toshiba, Hynix, and others.
- Supports all mandatory boot commands and selected optional commands
- Full access to spare area
SLC – Hamming Code
- One-Bit error correction
- Two-Bit error detection
MLC – BCH
- Configurable Blocks (512B, 1KB, 2KB)
- Supports 4-, 8- or 12- bit error correction
- Additional support of up to 32 bit error correction
Benefits
- Fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
Deliverables
- RMM Compliant Synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
