SD3.0 / SDIO3.0 / eMMC5.0 Host Controller IP – Advanced Info

The SD3.0/SDIO3.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:

  1. SD3.0
  2. SDIO3.0
  3. eMMC5.0

The SD3 / eMMC Host IP  handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD3 / eMMC5.0 Host IP.

Diagram

SD3/SDIO3/eMMC5.0 Host Controller IP from Arasan Chip Systems

Features

    Compliances

  • SD Host Controller Spec v3.0* (SDXC)
  • SDIO Spec v3.0
  • SD Memory Spec v3.01
  • eSD Memory Spec v2.1
  • eMMC Spec v5.0

    • IP Details

  • Supports eMMC5.0 latest features including

    • • HS400 high speed interface timing mode of up to 400 MB/s data rate
    • Field firmware update
    • eMMC device health report
    • eMMC production state awareness
    • Secure removal types
    • Sleep notification
    • Supports SDSC, SDHC and SDXC cards
    • Supports all UHS-I Operation Modes (DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50)
    • Supports UHS50 and UHS104 cards, Up to 104MBytes/sec read and write rates with 4 parallel SD data lines
    • Supports HS 200 and HS400 for eMMC devices, Up to 400MBytes/sec read and write rates with 8 parallel MMC data lines
    • Supports MMCPlus™ and MMCMobile™ cards
    • Supports Clock Tuning Mechanism
    • Host clock rate variable between 0 and 208 MHz for SD and up to 200 MHz for eMMC
    • Boot capability to boot directly from SD, eMMC cards
    • Supports Test Register to generate events by software
    • Supports non-DMA, SDMA, ADMA1, and ADMA2 modes
    • Supports both normal Boot mode and Alternate Boot Operation mode
    • Supports Hardware Reset Signal, Wakeup mechanism
    • Card detection (insertion / removal) during power down or when clock is turned off
    • Password protection of cards
    • Supports 1 and 4-bit SD modes and 1/4/8-bit MMC modes
    • Supports eMMC interrupt mode, 4KB sector size, Packed commands, RTC, Context ID, Data tag, Sanitize, Discard operations
    • Allows card to interrupt host in 1-bit, and 4-bit SD modes
    • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
    • Designed to work with I/O cards, read-only cards and read/write cards.
    • Supports read wait control, suspend/resume operation
    • Optional support for multiple slots; Optional SPI mode to handle legacy SD, MMC cards

Benefits

  • Fully compliant, silicon-proven core
  • Premier direct support from Arasan IP core designers
  • Easy-to-use industry standard test environment
  • Unencrypted source code allows easy implementation
  • Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass

Deliverables

  • RTL design in Verilog
  • UHS-I PHY GDSII
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documentation