UFS Device Controller IP

Arasan Chip Systems is a leading SoC IP provider of a complete suite of JEDEC UFS compliant IP solutions, which consist of IP cores, verification IP, software stacks and drivers, hardware platforms for software development and compliance testing, and optional customization services.

Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data storage. UFS is also adopted by MIPI as a data transfer standard designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, DSC, PMP, MP3, and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple but high-performance serial interface that efficiently moves data between a host processor and mass storage devices. USF transfers follow the SCSI model, but with a subset of SCSI commands. The Arasan UFS IP family consists of Host controller IP, Device controller IP, and M-PHY.

The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.

Diagram

UFS 1.0 device Diagram

Features

  • Compliant with the following specifications
    • JESD220 UFS 1.0 compliant
    • MIPI UniPro version 1.4
  • Interface supported
    • AXI
    • Optional AHB, OCP
    • High-performance M-PHY type 1
  • Core features
    • 1.5 Gbps max per lane
    • Multi-lane support [Optional - 1, 2, 3 or 4 lanes]
    • Low power with multiple power operating modes
    • Configurable Transmit and Receive FIFOs
  • Error detection and reporting. Support Data and Task management
  • Support for multiple commands and tasks

Benefits

  • RMM-compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents

Deliverables

• Verilog HDL of the IP Core
• Technical documents
• Gate count estimates available upon request
• Easy to use test environment
• Synthesis scripts

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