ONFI 3.1 PHY
The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips. ONFI seeks to standardize the low level interface. ONFI 3.1 is the standard for High-Speed NAND Flash interface. It has multiple modes of operation like SDR, NV-DDR and NV-DDR2 modes. Micron’s ClearNAND operation such as Queue page read and Program page pause, Program page resume, Program page delay are also supported.
ONFI 3.1 PHY extends the benefits of ONFI 3.0 and 2.3 standards. It provides a high speed interface supporting transfer rates up to 400 MT/s. It also supports the EZ-NAND interface. Lots of performance enhancing features like Interleaving operations, Multi-plane operations is supported.
ONFI 3.1 PHY incorporates the full TX/RX logic for NV-DDR2/NV-DDR mode of operation and is backwards compatible to SDR mode of operation. ONFI 3.1 improves on version ONFI 3.0 with more robust power sequencing to protect NAND flash, more flexible timing to support NAND usage in different topologies, improved parameters for testing, and other enhancements.
Included in the OFNI 3.1 PHY is a set of high speed I/O pads compatible to ONFI 1.8v 200 Mhz NV-DDR2 and 3v 100 Mhz NV-DDR.
- Compliant to ONFI revision 3.1 standard
- Silicon proven PLL to support all frequencies from 10MHz to 200MHz, and DLL to improve data sampling accuracy dynamically
- Include ONFI 3.1 I/O pads compatible to 1.8v NV-DDR2 400 MT/s and 3v NV-DDR 200 MT/s
- Supports NV-DDR2 mode of operation supporting up to 200MHz
- Supports NV-DDR mode of operation supporting up to 100MHz
- Supports legacy Asynchronous devices operating from 10MHz to 50MHz
- Can be used with any other ONFI digital controller
- Supports differential signaling of DQS and RE signals
- Supports four levels of drive strength as mentioned in the ONFI 3.1 standard
- Integrated soluiton including silicon proven PHY and I/O pads supprting 400 MT/s
- GDS-II Database
- LVS Netlist
- Physical Abstract Models (LEF)
- Timing Models (LIB)
- Process Specific Integration Guide