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USB 2.0 Device IP Core

USB 2.0 logo

The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhancements to the popular USB standard while offering backwards compatibility with billions of USB-enabled devices currently in the market.

 

 

The Arasan USB 2.0 compliant device core is available with an AHB/AXI, OCP or custom system bus interface. The USB2.0 device core supports 480 Mbits/s in High Speed (HS) mode and 12 Mbits/s in Full Speed (FS) mode of operation. Arasan provides designers with a comprehensive, silicon-proven configurable digital USB 2.0 Device solution that conforms to the USB 2.0 specification. It is designed to seamlessly integrate into any SoC design for an easy and cost effective solution. The Arasan USB 2.0 IP core supports up to 30 configurable IN/OUT non-control endpoints.

Each non-control endpoint has a controller for supporting interrupt, bulk and isochronous transfers. The dedicated control endpoint 0 handles USB defined command structure for Device Control. The USB 2.0 Device IP includes a multi channel DMA that can be configured to access any endpoint through registers. Optionally, it can interface with an external DMA controller. The USB 2.0 Device IP core provides an UTMI/ULPI interface that allows connection to any USB 2.0 transceiver module.  This product is listed in the USB.org database as ACS201.

Diagram

usb20-dev

Features

  • High speed support: 480 Mbit/s
  • Full speed support: 12 Mbit/s
  • USB 2.0 Compliant
  • High/Full speed support using 8/16 bit UTMI/ULPI interface
  • Master DMA implementation for each endpoint
  • Optional PIO Mode for each endpoint (can be used for Interrupt endoints)
  • System bus Master/Target clock
  • UTMI Interface Clock: 30/60 MHz
  • Endpoint Configuration
  • Configurable up to 15 Tx and Rx endpoints
  • Configuration options: Bulk, control, isochronous, interrupt
  • Dedicated control endpoint zero
  • Configurable dual port RAM shared between endpoints
  • USB Suspend/Resume support
  • 32/64 bit AXI, AHB or OCP bus interfaces

Deliverables

  • RMM-compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents
  • Simulation scripts

Benefits

  • Fully compliant to USB 2.0 specifications
  • Highly flexible and configurable
  • Ideal for easy and cost-effective device integration
  • Premier direct support from Arasan IP Engineering Team