10 Gigabit Ethernet Media Access Controller
Arasan’s (XGMAC) IP is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA. The 10 Gigabit Ethernet IP is designed for applications such as integrated networking devices, host bus adapters, PCI-Express Ethernet controllers, and Ethernet adapter cards.
The XGMAC operates at a speed of 10 Gbps in full duplex mode only. The XGMAC provides features that include transmit and receive message data encapsulation, framing, error code detection, dynamic FCS generation and calculation on frame by frame basis, automatic pad insertion and deletion to enforce minimum frame size requirements. The XGMAC also supports flow control operation by supporting generation and decoding of PAUSE control frames. The XGMAC also supports generation of Management frames on MDC/MDIO signals to communicate with an external PHY device. The XGMAC IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. An AHB/AXI master and a 64-bit scatter-gather DMA transfer packets between the internal FIFOs and the host memory to enhance system performance. The XGMAC IP supports the XGMII interface and a MDIO/MDC (Management Data Input/ Output and Management Data Clock) management interface provides control and management functions to external PHY devices.
The XGMAC IP also provides enhanced programmable features for minimizing applications complexity and pre/post message processing. The XGMAC IP supports MIB, SNMP, RMON, VLAN Q-Tag frame, and Jumbo frames. It also includes dynamic generation, checking, and stripping of FCS field, and automatic pad field insertion. Other features of the XGMAC IP includes generation and decoding of PAUSE control frames, frame boundary delimitation, frame synchronization, and error detection.
Diagram
Features
- Full-duplex mode at 10 Gbps
- Supports XGMII interface
- Independent 64-bit scatter-gather DMA with big/ little endian operation
- PAUSE frame based flow control in full-duplex mode
- MDIO/MDC management interface
- 802.3 compliant MIB, SNMP, RMON management
- support
- Configurable transmit and receive FIFOs
- Supports Jumbo frames
- Supports Magic Packet or WakeonLan packets
- Optional , PCIe, PCI, or custom bus interfaces
Benefits
- Fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
Deliverables
- RMM Compliant Synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
