I2C Master / Slave Controller IP Core
with AHB Interface
Overview
The synchronous I2C interface is a block that interconnects an APB bus. The APB – I2C Bridge interfaces to the APB bus on the system side and the I2C bus. The APB interface is used to easily integrate the Bridge Controller for any SOC implementation.
The APB – I2C is a master/slave interface that enables synchronous serial communication with the other master or slave I2C peripherals having I2C compatible interface. The controller performs the following functions:
- Parallel-to-serial conversion on data written to an internal 8bit wide, 1024 deep FIFO.
- serial-to-parallel conversion on received data, buffering it in a similar 8-bit wide, 1024 deep FIFO
Diagram
Features
- Compliant with I2C specification Version 2.1
- Supports a simple bi-directional 2-wire bus for efficient for inter-IC control
- Programmable as I2C Master mode
- Programmable as I2C slave mode
- Supports a Clock generation circuitry to derive I2C clock from APB clock
- Supports various transfer speeds up to 1Mbps
1.2 APB Interface
- Compliant with AMBA [Rev2.0] for easy integration with SOC implementations
- Supports APB bus for varying frequency range
- Supports Programmed IO and External DMA modes.
- Has FIFO (Configurable) to accelerate the data transfers from and to I2C and APB.
Benefits
- Fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Un-encrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured
Deliverables
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
- Simulation scripts
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