I2S Controller IP Core
The Arasan I2S Controller IP Core is a two-channel I2S serial audio controller compliant to the Philips* Inter-IC Sound specification. The I2S bus is used for connecting audio components such as speakers, DACs, or audio subsystems.
The Arasan I2S Controller IP Core provides a 32-bit parallel processor bus as the application interface. The controller’s I2S interface consists of one transmitter and one receiver. Each channel can be programmed as an I2S master or an I2S slave. The Bit Clock (BLCK) and Left and Right Clock (LRCK) provide synchronization for the transmit and receive data. The I2S Controller IP supports 44.1KHz audio samplingrates. DAC/ADC resolution is configurable from 8-bit to 32-bit. The included transmit FIFO and receive FIFO handle data transfers between the I2S interface and application interface. These two interfaces can be operated in two independent clock domains. The I2S Controller also includes interrupt support for reporting FIFO and other conditions. The I2S Controller IP supports a 32-bit parallel bus interface. AHB, PCI or other custom specific buses can also be provided upon request.
Diagram
Features
- Complies with Philips* I2S Specification
- Supports two I2S channels
- Simultaneous audio playback and recording
- Supports configurable 8/16/24/32 bit DAC/ADC resolution
- Supports 44.1KHz audio sampling frequencies
- 32-bit parallel processor bus
- Interrupt support for FIFO transfers
- Supports 256 sampling frequency operating modes
- Other custom buses available upon request
Benefits
- Fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Un-encrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured
Deliverables
- RMM Compliant Synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
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