SPI AHB IP Core

The SPI – AHB bridge enables an AHB host to access a serial device at high-speed through the SPI interface. The controller can be used in applications such as flash memory card and digital camera. Both AHB and SPI support master and slave modes. The AHB – SPI bridge performs either parallel-to-serial conversion or serial-to-parallel conversion with a maximum throughput of 50 Mbit/sec. A 32-bit x 32-bit transmit FIFO and a 32- bit x 32-bit receive FIFO serve as the data buffer to coordinate data flows between the AHB and SPI interfaces. The AHB master consists of a DMA controller to enhance the system performance. A SPI Clock Generator is included to provide adjustable input clock to the SPI controller. A SPI clock frequency from 500 KHz to 50 MHz can be selected. The Status and Interrupt Generator provides data transaction information to the AHB host processor that reflects the FIFOs and DMA states. The SPI controller consists of one SPI master and one SPI slave and it can be programmed by an AHB host to support the TI, Motorola, or National SPI protocol. Full SPI duplex mode is supported. The Arasan High Speed SPI – AHB IP Core is an RTL design in Verilog that implements an SPI – AHB controller on an ASIC, or FPGA.The Arasan High Speed SPI – AHB IP Core has been widely used in different applications by major chip vendors.

Diagram

spi-ahb

Features

SPI Bus

Compliant with Motorola SPI specification
Compliant with TI SPI specification
Compliant with National SPI specification
Supports both SPI master and SPI slave Operations
Maximum 50 Mbit/sec data throughput
Pre-scaling for programmable clock rate from 500 KHz to 50 MHz
Supports full-duplex mode

AHB Bus

Compliant with AMBA revision 2.0 specification
Supports AHB bus for varying frequency range from 1 MHz to 100MHz
Supports Bus master DMA modes.
Supports both AHB master and AHB slave modes.
Supports interrupts.
32 x 32 bytes transmit and receive FIFOs for high performance AHB - SPI data transfers.

Benefits

Fully compliant core
Premier direct support from Arasan IP core designers
Easy-to-use industry standard test environment
Un-encrypted source code allows easy implementation
Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured

Deliverables

RMM Compliant Synthesizable RTL design in Verilog
Easy-to-use test environment
Synthesis scripts
Technical documents