eMMC 5.1 Device Input/Output | Arasan Chip Systems

eMMC 5.1 Device I/O Pad

Arasan Chip Systems’ eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50 specification. It is backward compliant with eMMC4.51 and earlier versions of the specifications. This allows the designers of the SoC to easily support the EMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 hosts.

The eMMC 5.1 Device I/O PAD is a multipurpose PAD which can be programmed to operate in different modes:

Output with predetermined source/ sink impedance
Open drain
Input
Tristate
Weak pull up or pull down

The PAD mode of operation is determined by DR_EN, OD_EN, REN, and PU control signal. When the push-pull mode is selected, the source/sink impedance can be programmed to 50, 33, 66, 100 or 40 Ohms. DR_TY control bits are used to select the desired source/sink impedance. The source/sink impedance variation with PVT exceeds 25 % of its nominal value, trimming bits are provided to greatly reduce the variation. RTRIM bits are used for this purpose. ARASAN CAL I/O can be used to automatically reduce the variation to less than 8%.

Features

The following are the high level features of the ACS eMMC5.1 PHY:

Designed for seamless integration with ACS’s eMMC5.1 Device Controller.
Supports HS400, HS200, DDR50 and legacy operating modes.
Includes EMMC I/O PADS with ESD protection structures.
The ACS EMMC I/O PADS are designed to meet eMMC5.1 HS400 specifications.
ACS eMMC5.1 PHY is available in the latest TSMC technology nodes.
The design is intended for core supply VCORE +/-10% and I/O supply VCCQ +/-10%.

Arasan’s general purpose I/O PADs are multipurpose PADs that can be programmed to operate in different modes: 1) Output with predetermined source/sink impedance, 2) Open drain, 3) Input, 4) Tristate and 5) Weak pull up or pull down. The I/O PADs are specially designed to seamlessly integrate with Arasan’s eMMC 5.1 and eMMC 5.0 host controller IP. Arasan introduced the industry’s first HS400PHY in 2013 on multiple nodes and since then the engineering team has been working diligently to keep up with the latest versions.