The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code validated for compliance with the standard, a comprehensive test environment & compliance suite for validation of the IP, a Sound wire hardware development kit for FPGA prototyping and interoperability testing, a Sound wire protocol analyzer and the complete Soundwire software stack.
The IP is fully configurable for the number of (options like endpoint, audio channels etc.) to meet a wide range of audio applications. Soundwire is suited for small, very cost-sensitive audio peripherals such as amplifiers and microphones.
The major differences between v1.0 and v1.1 are:
●Configurable port direction – allows the Data Port to be either Sink or Source at run time
●Reduced Data Port – specifies certain optional features and registers to provide more flexibility compared to Simplified Data Port
●BRA Failure interrupt
Diagram
Features
Compliant with latest draft MIPI SoundWire specification version 1.1
Flexible configuration for optimal gate count and power
Single SoundWire DATA Lane and a single Data port for simple applications
Supports up to 8 DATA Lanes for high bandwidth applications
Supports multiple DATA Ports for more complex audio devices and channel configurations
Flexible DATA Port SoundWire Lane mapping
Implements all three layers and provides a simple application interface
PHY
Framer
Transport (Data and Control Ports)
Application Interface
PHY
Configurable number of DATA lanes (1–8)
Modified NRZI Data coding
Test modes
Bus clash detection
Framer
Synchronization
Multiplexing/De-multiplexing of payload streams from/to Data ports
Parity generation & checking
Supports Clock Stop
Forms & formats the Control payload for Register read/write commands
Transport (Data and Control Ports)
Configurable number of Data ports (1 – TBD)
Simple FIFO interface to pass samples from/to application
Programmable direction and FIFO depths
Data Port 0 for Bulk Payload Transport Protocol (BPT)
Supports Bulk Register Access (BRA)
Supports all the standard data port attributes & controls
Implements Data Port Registers(DPN_*) for each port
Programmed/accessed via AHB slave interface
Implements Control Port registers
Data Port Lane mapping
Application/Client Interface
Simple FIFO interface to pass audio samples from/to application for each Data port
Programmable direction and FIFO depth
APB Slave interface
Access to internal Registers
Pass register Read/Write commands and data of SoundWire slaves
Other interface options (AHB, SRAM, Custom) available
Interrupt line
Deliverables
Verilog HDL of the IP Core
Synthesis scripts
Verification environment
User guides for design and verification
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
