The Arasan SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.
SLIMbus has a TDM channel allocation structure for control messages and data. When its Framer is active, the device drives the SLIMbus clock, creates the SLIMbus frames, and enables the other SLIMbus devices and the SLIMbus host to synchronize and share the available bandwidth.
SLIMbus Device Controller IP Core contains a configurable generic device that transfers data to and from remote SLIMbus components and legacy interfaces, like I2S, I2C, and SPI, or interface directly to audio DAC’s and ADC’s through the Generic FIFO Interface. One or more port pairs of the generic device can be used for each kind of peripheral interface, up to a maximum of 16.
At a system level, this IP operates under the control of a SLIMbus host, whose active manager and associated software stack monitors the characteristics and status of the SLIMbus device, and configures its registers and access to the bus accordingly.
Diagram
Features
Compliant with MIPI SLIMbus Specification version 2.0
Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
Small footprint
Contains full-featured active interface device, with support for
Dynamic channel allocation and management
All SLIMbus Core Messages
Error handling and recovery, as defined in the MIPI SLIMbus specification
Embedded framer which can be active or passive, and supports SLIMbus clock generation handoff to/from framers in other components, with support for
Clock Gears 1 to 10, either as clock source or clock receiver
Maximum of 28.8 MHz bit-serial rate
Dynamic SLIMbus clock frequency scaling and clock pause/resume minimizes power
Contains one generic device with up to 8 active port pairs; each port supports
sochronous, Pushed, Pulled, Asynchronous Simplex, Extended Asynchronous Simplex and Locked transport protocols over SLIMbus with data segment size of 1 to 31 slots
Interface options to peripheral components or devices
Generic FIFO Interface
Audio or peripheral data sample sizes of 8, 16, 24 or 32 bits
Different port pairs can have different sampling rates
I2S for Audio channels
SPI or I2C for interface to other peripherals or microcontrollers
Deliverables
Verilog HDL of the IP Core
Synthesis scripts
Verification environment
User guides for design and verification
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
