Arasan Chip Systems a leading provider of mobile storage IP will demonstrate its Total IP Solution for the eMMC and SD Card standards with it’s latest TSMC 12nm PHY IP Test Chip.
Aug 1, 2018, San Jose, CA: Arasan today announced that they will demonstrate their latest products, the SD Card UHS-II PHY and eMMC 5.1 PHY on a TSMC 12nm test chip. The PHY IP will be seamlessly integrated with our SD Card Host IP and eMMC 5.1 Host IP respectively and Arasan will demonstrate an end to end solution. The demonstration platform will also have our software stacks and HDK forming the Total IP Solution for eMMC and SD Card standards.
Arasan joined as an executive member of the SD Association in 2001. The first IP Product we announced for the SD standards was the SDIO Device Controller IP followed by the Standard SD Host Controller IP. The SD / SDIO Card IP Product line remains Arasan’s most successful product line to date.
Arasan has also been supporting the JEDEC eMMC standard since the time it, like the SD Card was the removable storage Multi Media Card (“MMC”). MMC was promoted by the Multimedia Card Association which then merged with JEDEC in 2008. eMMC has grown rapidly to become the preferred embedded storage standard of choice for mobile applications including a majority of mobile phones in the market today.
Availability
The SD Card UHS-II PHY and eMMC PHY IP are available immediately for 12nm, 16nm, 28nm and 40nm SoC Designs.
About Arasan
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile, automobile and Drone SoC’s. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for mobile connectivity and storage standards. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.