Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard. It offers reliable communication at moderate data rates and is widely used in automotive applications such as powertrain control, chassis control, body electronics, and in-vehicle networks. The simplicity, robustness, and proven track record of Classical CAN make it suitable for applications that do not require high data rates or large payload sizes. Arasan’s CAN IP Controller Core performs serial communication as per CAN IP 2.0 Specifications. It supports full CAN IP 2.0 (both CAN IP 2.0A and 2.0B). The design implements the BOSCH CAN IP Message Transfer Protocols 2.0A (which is equivalent to CAN IP 1.2 and covers standard message formats with 11-bit identifiers); and 2.0B which covers both standard and extended message formats (both 11-bit and 29-bit identifiers). Arasan’s CAN IP Controller core is easy to integrate with the Host processor using an AMBA-AHB standard interface. This highly configurable design supports programmable Interrupts, data and baud rates, acceptance filters & buffering schemes specific to the application By leveraging the appropriate CAN bus standard within an SoC, automotive systems can benefit from optimized communication performance, enhanced bandwidth, and the ability to meet the specific requirements of their target applications.
Fig 1 Block Diagram of CAN IP2.0 Controller
FEATURES
CAN Controller IP Specifications Support
• Full CAN IP 2.0, both BOSCH CAN IP 2.0A and CAN IP 2.0B • Fully programmable from 128Kb/sec to 1Mbits/sec Reliability, Availability, Serviceability (RAS) • Error Diagnostics for all error types like Bit error, Stuff Error, CRC error, Form Error and Acknowledgement Errors • For safety extensive error detection support such as Monitoring, CRC, Bit Stuffing and Message frame check • Loopback test for self-testing option • Hot plug-in, automatic bit-rate detection support • Programmable error threshold detection Configurable Message Buffering & Filtering • Configurable Receive Buffers, Low-priority Transmit Buffers • FIFO Mode and Priority Modes for Transmit Buffers Ease of Integration, Usage & Porting • AMBA-AHB Standard Interface • Optional Multi-CAN IP Wrapper for controlling multiple CAN IP Bus Nodes using a single host CAN IP Controller • Easily can be ported to various FPGAs & ASIC Designs Compliance Check • Multiple 3rd Party CAN IP2.0 Verification IP Protocol Compliance checked
DELIVERABLES
• System Verilog RTL Source Code • A simplified Testbench with simulation models to run initial set of tests after release • Synthesizable Netlist • Synthesis Scripts and exception lists • Timing Report • Protocol Compliance & Coverage Report • Sample Firmware with Drivers • Application Notes
CAN FPGA Demo video Link:
Note*: ” License does not include the CAN Protocol License and CAN Trademarks” CiA has a long and fruitful relation to Arasan Chip Systems, Inc. Since 2013, we have been in contact regarding CAN and CAN FD IP cores. Since 2021, The Company is a member of the nonprofit CiA association and part of the CiA community with more than 700 members. We appreciate the support by Arasan Chip Systems,” said Holger Zeltwanger, CiA Managing Director since 1992.
