SD Card v.3.0 / eMMC v.4.51
SD Card / SDIO Card Combo Device IP
SD / SDIO Card Combo Device IP core is SD memory controller and a SDIO controller with an AHB interface. Combining with the optional Arasan NAND Flash Controller IP, the SD/SDIO Combo Device IP provides an integrated SD memory Card solution for designs that utilize NAND flash memory.
The SD Card Combo IP is a full/high-speed card suitable for memory cards and I/O card applications such as WLAN, Bluetooth, and mobile devices with low power consumption. The full-speed card supports SPI, 1-bit, and 4-bit SD transfer modes at a full clock range of 0-50Mhz. The Arasan SD/SDIO Combo Device IP has an AHB interface, which allows the ARM processor to configure the operational registers resided inside the AHB slave core.
To support NAND flash memory, Arasan provides an optional NAND Flash Controller for direct interfacing with the SD Card Combo Controller IP. The Arasan NAND flash controller handles all command, address, and data sequences. It also manages all the hardware protocols and allows the users to access the NAND flash memory simply by reading or writing into the Operational registers. The Arasan NAND flash controller acts as a master or a slave device on the AHB bus.
Features
- Compliant to SDIO card specification version 3.0 and SD Memory Card Physical Layer Specification version 3.0
- AMBA AHB Specification Rev 3.0
- Supports SDHC and SDHS cards
- Supports SDHC combo cards
- SD Interface
- Supports SPI, 1-bit, and 4-bit SD modes
- Allows card to interrupt host in SPI, 1-bit, and 4-bit SD modes
- Up to 200-Mbit/s read and write rates using 4 parallel data lines
- 0 to 50 MHz host clock
- CRC7 for commands, and optional CRC16 for data integrity checking in SPI mode
- Application specific commands
- Comfortable erase mechanism
- Password protection of cards
- Write protect feature using mechanical switch
- Built-in write protection features
- Hot card insertion and removal
- Switch function command supports highspeed
- Card responds to direct read/write (IO52) and extended read/write(IO53) transactions
- Read Wait Control, Suspend/Resume operations
- Supports up to 8 banks of NAND flash devices
- Programmable access timing
Deliverables
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
Benefits
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
