2.5gsps C/D-PHY Combo ASIC from Arasan provides C-PHY support for FPGA with Arasan’s CSI-2 and DSI-2 Tx and Rx IP.

Arasan Sirius Test Chip supports MIPI C-PHY v1.1 @2.5 Gsps and MIPI D-PHY v1.2 @2.5 Gbps, the Test Chip is fabricated on TSMC 28nm process. This C/D PHY Combo ASIC can be configured as either a D-PHY℠ with one clock and up to four data lanes, or a C-PHY℠ with up to 3 trio lanes. Area overhead to support both modes is minimized by reusing the D-PHY℠ blocks and high-speed IO’s.

Figure 1 Arasan C/D PHY Test Chip Block Diagram

This C/D PHY ASIC enables customers to prototype their CPHY and DPHY based projects using MIPI DSI or CSI IP Cores.  We have implemented the controller (CSI2 / DSI2) with PPI interface on FPGA and which is connected to the C/D PHY ASIC. We used FMC connectors to connect the controller (FPGA) and PHY (ASIC).

Arasan C/D-PHY ASIC interfaces seamlessly to both D-PHY℠ and C-PHY℠ based sensors over its MIPI CSI-2® IP Core and MIPI Displays that are increasingly adopting C-PHY over our MIPI DSI-2℠ IP core.

Figure 2 C/D PHY FPGA board setup

This combo PHY provides a low-power and high-performance interface for platforms ranging from processors to peripheral devices for mobile, automotive, AI and IoT applications. It inter-operates seamlessly with Arasan Chip Systems CSI-2® and DSI-2℠, and offers built-in test capabilities including PRBS generator and internal loopback to support cost effective tests for high volume manufacturing.

Here is a video showcasing our Test Chip platform in action: https://youtu.be/lmC50LjFwHQ

The tester is manufactured by Test Evolution and OEM’d by LeCroy.

Note: 4.5gsps ASIC is also available in limited quantities to selective customers

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