Arasan UFS on FPGA using built in SERDES

Arasan UFS + MPHY DFE IP implemented on FPGA using Xilinx build in Giga Transceiver to prototype. Below is the block diagram for the FPGA Platform.

Figure 1 FPGA Platform

The UFS validation system is basically is a pre-configured Linux machine with a PCI-e based FPGA board along with MPHY daughter card, loaded with Arasan UFS IP. The HVP is pre-loaded with UFS software stack and applications. We used Xilinx Virtex 7 FPGA(XC7VX485T-ffg1761) board for our UFS 3.0, UFS 2.1 and UFS2.0 Platforms.  UFS 3.1 and UFS 4.0 our customers used Xilinx Ultra scale FPGA (xcvu13p-fhga2104) Boards.

Figure 2 UFS HVP

MPHY – FPGA Glue Logic is mainly used as a SERDES for PWM mode and to generate control signals for Arasan MPHY Daughter board.

The Arasan M-PHY DFE can be integrated with any internal SERDES supporting M-PHY speeds of 6 or 12 or 24gig.

Link to Jingce Press release:

https://www.prweb.com/releases/arasan-and-xilinx-announce-their-design-win-in-providing-a-total-ufs-3-0-solution-to-wuhan-jingce-893662373.html

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