Overview
Arasan’s xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs. When coupled with the ACS xSPI PHY, the combined IPs are able to interact with SPI, Dual SPI, Quad SPI, Octal SPI, and xSPI devices at the full 200 MHz data rate. This includes both HyperRAM and HyperFlash protocols. Both single and dual data rate modes are supported. The xSPI Master controller IP supports flash devices, whereas the xSPI/PSRAM controller has been designed to support SRAM types of devices using the same interface.
• Can be used with both the xSPI/PSRAM and xSPI Master host controller IPs
• A PHY is required to support the high speed xSPI modes (> 50 MHz)
• Designed to support JESD 251
• Requires a reference clock frequency between 170 and 220 MHz
• Supports a nominal 200MHz data rate, provided by the reference clock, as well as integer divisions of it
• Includes a DLL to facilitate clock and data strobe phase delays in units of 625 ps
These offsets are required to generate the 90-degree phase offsets required of the xSPI protocol, as well as to adjust the return data sample timing to move it closer to the center of the data eye.
• Includes a small asynchronous FIFO on the read path for the purpose of accepting strobe–clocked data.
• Using the four chip select pins, the xSPI PHY can drive a shared bus with up to four memory chips present on it
• Supports extra pins, to include the interrupt detect (INTN), Error Correction Status (ECSN), write protect (WPN), reset (RESET N), and reset return (RSTO) wires used by some devices. These pins are optional in any implementation, and may not necessarily be used by all designs.
Features
• Supports for both the xSPI/PSRAM and xSPI Master host controller IPs.
• Support the high speed xSPI modes (> 50 MHz).
• Designed to support JESD 251.
• Requires a reference clock frequency between 170 and 220 MHz
• Supports a nominal 400 MT/s data rate, provided by the reference clock, as well as integer divisions of it
• Includes a DLL to facilitate clock and data strobe phase delays in units of 625 ps. These offsets are required to generate the 90-degree phase offsets required of the xSPI protocol, as well as to adjust the return data sample timing to move it closer to the center of the data eye
• Supports On Chip Resistance calibration with retrigger option to re-calibrate the driver resistance if needed
• Option to manually force the calibration codes by bypassing the calibration block
• Provided a dedicated port to tap out the calibration code in the PHY level that can be used for calibrating external PHY’s technology resistor if needed
• Includes a small asynchronous FIFO on the read path for the purpose of accepting Strobe–clocked data
• Using the four chip select pins, the xSPI PHY can drive a shared bus with up to four memory chips present on it
• Supports extra pins, to include the interrupt detect (INTN), Error Correction Status (ECSN), write protect (WPN), reset (RESET N), and reset return (RSTO) wires used by some devices. These pins are optional in any implementation, and may not necessarily be used by all designs.
• Supports Push-Pull driver with different drive strength.
• Provided an Optional weak pull-up resistor to avoid the floating IO