The Arasan I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices. The I3C Host Controller IP Core provides a 32-bit AHB bus as the application interface to configure and control the I3C Host Controller IP Core. The I3C Host Controller IP can be easily integrated into an SOC to provide the required I3C functionality. Also, the I3C Host Controller IP provides direct signaling to connect to the IO Buffers (SCL and SDA).
The I3C Host Controller implements support for legacy I2C Device Controllers, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support. The I3C Host Controller supports the required SDR mode with Clock frequency of up to 12.5 MHz and also the HDR modes as defined by the I3C Specification. The included FIFO (Configurable) is used to handle data transfers between IP and the external Device Controllers.
Diagram
Features
Compliant with MIPI I3C Specification v1.2
Compliant with MIPI I3C HCI Specification v1.1
Supports up to 12.5 MHz operation using Push-Pull
Supported features,
Open-Drain and Push-pull type transactions (as required)
Supports legacy I2C devices
Dynamic addressing while supporting Static addressing for Legacy I2C devices
Legacy I2C messaging
I2C-like Single Data Rate messaging (SDR)
High Data Rate messaging modes (HDR-DDR, HDR-TSP, HDR-TSL modes)
Reception of In-band Interrupt support from the I3C Device Controllers
Reception of Hot-Join from newly added I3C Device Controllers
Support for Target reset
Support for group addressing
AHB Target Interface for Configuring/Controlling the IP with Interrupt output
AHB Interface for Host Controller DMA access
Support for up-to Eight rings in DMA mode and configurable as per the application requirement
Support for JESD403-1 Sideband Interface
Configurable FIFO sizes for PIO, DMA, Command, Response, and IBI Queue. Common FIFOs are used for both PIO and DMA modes.
Deliverables
RMM compliant synthesizable RTL design in Verilog
Easy-to-use Test environment
Synthesis scripts
Technical documents
Validated with 3rd Party Device Controller VIP and available as an additional option
