The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and various sensor devices. The I3C interface is intended to improve upon the features of the I2C interface, preserving backward compatibility. This I3C defines a standard multi-Drop interface between Host processors and peripheral Devices (e.g., sensors). Implementing the I3C Specification greatly increases the flexibility system designers have to supplant incumbent interfaces (i.e., I2C, SPI, UART) and support a wide array of Devices of increasing complexity and diversity in their system (e.g., sensor subsystem) and at as low a cost as possible.
I3C PHY
Diagram
The I3C PHY is functionality of the MIPI I3C v1.2. It has two primary blocks, the Digital Front End (DFE) and Analog Front End (AFE).
Features
- Compliant with MIPI I3C specification Version 1.2
- Support data transfer up to 12.5 MHz operation during Push-Pull
- Support open drain mode
- Support Single Data Rate messaging (SDR)
- Support High Data Rate Messaging Modes
- HDR-DDR for Double Data Rate
- HDR-TSL for Ternary Symbol Legacy-Inclusive-Bus
- HDR-TSP for Ternary Symbol for Pure Bus
- Support legacy I2C devices
- Support Dynamic Addressing while supporting Static Addressing for Legacy I2C devices
- Support Reception of In-band Interrupt support from the I3C Slave devices
- Support Reception of Hot-Join from newly added I3C Slave devices
- Support Target reset
- Support Group Addressing
- Support Synchronous Timing Support and Asynchronous Time Stamping