Arasan Chip Systems is a leading SOC IP provider of a complete suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, software stacks and drivers, protocol analyzers, hardware platforms for software development and compliance testing, and optional customization services.
The MIPI compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.
Arasan IP Core that functions as a MIPI CSI-2 Transmitter, which typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link to a CSI2 Receiver in the applications processor. The Arasan CSI-2 combo IP is MIPI-compliant and provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
Diagram
Features
Compliant with the following MIPI specifications:
CSI2 specification v2-1
DPHY specification v2-1
DPHY specification v1-2
CPHY specification v1-2
CSI-2 Combo Transmitter Core features:
Use of either D-PHY/C-PHY by user configuration
Lane Configurability depending on the bandwidth requirements of the application, up to 8-lanes for DPHY and up to 3-lanes for C-PHY
Connectivity to DPHY/CPHY through MIPI PPI Interface
High Speed (HS) receiver rates of 182Mbps (80Msps) to 6840Mbps (3Gsps) per lane with C-PHY interface
High Speed (HS) receiver rates of 80Mbps to 1500Mbps per lane without calibration, 1500Mbps to 2500 Mbps with skew calibration and 2500Mbps to 4500Mbps with equalization in D-PHY interface
Supports for Alternate Low Power State (ALPS) in CPHY mode
Support for Ultra Low Power Mode (ULPS)
Support for Continuous and Non-Continuous Clock Mode
Pixel formats supported
RAW data type
YUV data type
RGB data type
All user Defined data types / JPEG
Generic 8-bit long packet data types
Supports Data Type Interleaving
Supports Virtual Channel Interleaving
Supports Virtual Channel extension as 16 VCs in DPHY mode and 32 VC’s in CPHY mode
Support for optional feature Data scrambling
Support for CPHY lane deskew
Support for Packet spacing LRTE/EPD feature (optional)
Pixel Level Input Interface for Image Sensor
Supports Header and Payload Checksum
Configurable for two mode of operation
Store and Forward Mode – Stores the full pixel packet before
Cut through Mode – Initiates the HS transmission to D/CPHY as soon as the pixel information is received. Makes use of very shallow memory.
Supports Multi Pixel Mode – Multiple Pixels per clock to bring down the sensor clock frequency to support higher resolution applications
PPI Data Lane swapping as per user configuration
Optional support for Compressed data formats
Host interface for register configuration and monitoring,
Used for programming both CSI-2 and PHY related registers. Reserved address space [0x00 – 0x0F] for the PHY related
Optional support for the AHB/APB Interface
Deliverables
Verilog HDL of the IP core
User guide
Synthesis scripts
Lint report
CDC report
Verilog test suite
Gate count estimation available upon request
Benefits
Fully compliant to MIPI standard
Small footprint
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
