Arasan’s Soundwire PHY consists of input and output buffers to receive and transmit data and clock. The output buffer can be programmed for different drive strength and slew rate to meet the specification requirements for different loads. There is also a bus keeper to maintain the voltage level for some required conditions for the data. When it operates as Master, it includes an input and output buffer for the clock signal. The output buffer sends the clock signal to all other Slave interfaces. When it operates as Slave, the clock output buffer is disabled and it only receives clock from outside. A delay cell is used to set the delay for High-Z to driving data timing. This IP uses synchronous turn-off method for data output. It has also capability to operate as Basic-Phy or High-Phy.
Soundwire PHY
Features
- Compliant with MIPI specification for SoundWire V1.2
- Data input buffer
- Data output buffer with programmable drive strength and slew rate control
- Data bus keeper to maintain the voltage level
- Clock output buffer with programmable drive strength and slew rate control
- Clock input buffer
- Capability for synchronous turn off data output
- Delay cell for High-Z to driving data timin
- Capability to operate as Master or Slave
- Capability to operate as Basic-Phy or High-Phy
- Capability to switch from SoundWire mode to IO mode operating up to 50MHz