Arasan PHY’s are readily available and in production with multiple foundries from 5nm to 180nm. Our PHY’s are designed for low power on the most advanced nodes for the mobile market while also targeting the automobile market on specialized nodes where extreme temperature tolerance is required.
- MIPI C-PHY v1.2 D-PHY v1.2 – C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to DPHY. Arasan’s CPHY-DPHY combination provides a 3 channel C-PHY v1.2 and a four-lane D-PHY v1.2 in a single IP core. This allows a seamless implementation allowing the interface to D-PHY based sensors or C-PHY based sensors. Symbol encoding effectively transfers 2.286 bits per symbol compared to 1.0 bits per lane for D-PHY. The C-PHY (v1.2) operates at 3GS/s, whereas the D-PHY V1.2 (2.5Gb/s). A four-lane D-PHY V1.2 provides 10Gbps.
- MIPI C-PHY – physical interface for CSI-2 providing 5.7Gbps per lane of bandwidth The MIPI C-PHY V1.0 improves throughput over a bandwidth-limited channel, allowing more data without increased signaling clock. It is intended to be used for the camera interface (CSI-2 v1.3) and display interface (DSI v1.2). The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.
- MIPI D-PHY V1.2 – physical interface for CSI-2 and DSI providing 2.5Gbps per lane of bandwidth Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital (PPI) interface to control the I/O functions.
- MIPI M-PHY 4.1 G4 & G3 – M-PHYs is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
- MIPI M-PHY 3.1 – physical interface for UFS, providing up to 5.9Gbps of bandwidth Arasan’s M-PHYs are of Type 1, which apply to UFS protocols. The Multi-gear M-PHY 3.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
- SD UHS-II 4.1 – physical interface for SD 4 Arasan’s SD 4.1 UHS-II PHY operates in both the Full-duplex and Half-duplex modes. It includes a 8b/10b encoder/decoder. The controller side interface of the UHS-II PHY operates in the range from 39MB/s to 156MB/s. The default data lane D0 is used for downstream connection and the D1 lane is used for the other direction. An 8b/10b coding scheme is used. To improve testability, the SD 4.1 UHS II PHY implements the standard loopback paths.
- eMMC HS400 PHY – physical interface for eMMC 5, providing 3.2GB/s of bandwidth Arasan’s eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 when rectified and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications. This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.
- ONFI 3.2 PHY – physical interface providing 4 (8) GByte/sec for x8 (x16) data bus ONFI 3.2 PHY extends the benefits of ONFI 3.x and 2.3 standards. It provides a high-speed interface supporting transfer rates up to 400 MT/s. It also supports the EZ-NAND interface. Lots of performance-enhancing features like Interleaving operations, Multi-plane operations are supported.
- ONFI 4.1 PHY – physical interface providing 8 (16) GByte/sec for x8 (x16) data bus ONFI 4.1 PHY extends the benefits of ONFI 3.x and 2.3 standards. It provides a high-speed interface supporting transfer rates up to 800 MT/s. It also supports the EZ-NAND interface. Lots of performance-enhancing features like Interleaving operations, Multi-plane operations are supported.
- USB 2.0 PHY – physical (external) interface for USB 2 The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use with host, embedded host, On-the-Go (OTG) and function controllers. Its high speed, mixed-signal circuitry supports 480 Mb/s USB 2.0 High Speed (HS) traffic, while remaining backward compatible with USB 1.1 legacy protocol for 12Mb/s Full Speed (FS) traffic and 1.5Mb/s Low Speed (LS) traffic.
- USB 2.0 HSIC PHY – physical (chip to chip) interface for USB 2 USB 2.0 HSIC PHY is a 2-signal (strobe, data) source-synchronous serial interface which uses 240Mhz DDR signaling to provide High-Speed 480Mps USB transfers which are 100% host driver compatible with traditional USB cable-connected topologies. Full-Speed (FS) and Low-Speed (LS) USB transfers are not directly supported by the HSIC interface (an HSIC enabled hub can provide FS and LS support, as well as IC_USB support)