Arasan’s eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications. This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.
eMMC 5.1 HS400 PHY IP consists of hardened PHY IP and RTL block code. The hard-macro consists of analog IPs, such as eMMC 5.1 interface Pads, Impedance Calibration Pad, an analog DLL, and the DLL wrapper. The RTL Block code includes Arasan’s Host/Device controller.
To assist with eMMC 5.1 IP integration, Arasan provides all of the back-end views of eMMC 5.1 GPIO Pads and CALIO Pad integrated with TSMC ESD protection structure for I/O VDDQ, VSSQ, and Power Clamps.
Features
Suitable for Transmitter, Receiver, and Data Strobe pins
I/O voltage: 1.8V or 3.3V
Core voltage: 0.9V
Deliverables
GDSII database
LVS Netlist
Physical Abstract Model (LEF)
Timing Models
Behavioral Models
Design Integration Guide
Technical Documentation
Benefits
Silicon proven, fully compliant core
Premier direct support from Arasan IP core designers
Arasan’s general purpose I/O PADs are multipurpose PADs that can be programmed to operate in different modes: 1) Output with predetermined source/sink impedance, 2) Open drain, 3) Input, 4) Tristate and 5) Weak pull up or pull down. The I/O PADs are specially designed to seamlessly integrate with Arasan’s eMMC 5.1 and eMMC 5.0 host controller IP. Arasan introduced the industry’s first HS400PHY in 2013 on multiple nodes and since then the engineering team has been working diligently to keep up with the latest versions.
