eMMC 5.1 PHY

eMMC 5.1 HS400 PHY

 

Arasan’s eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications. This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.

eMMC 5.1 HS400 PHY IP consists of hardened PHY IP and RTL block code. The hard-macro consists of analog IPs, such as eMMC 5.1 interface Pads, Impedance Calibration Pad, an analog DLL, and the DLL wrapper. The RTL Block code includes Arasan’s Host/Device controller.

To assist with eMMC 5.1 IP integration, Arasan provides all of the back-end views of eMMC 5.1 GPIO Pads and CALIO Pad integrated with TSMC ESD protection structure for I/O VDDQ, VSSQ and Power Clamps.

Diagram


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