eMMC5.1 Device I/O

eMMC 5.1 Device I/O Pad

Arasan Chip Systems’ eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50 specification. It is backward compliant with eMMC4.51 and earlier versions of the specifications. This allows the designers of the SoC to easily support the EMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 hosts.

The eMMC 5.1 Device I/O PAD is a multipurpose PAD which can be programmed to operate in different modes:

  • Output with predetermined source/ sink impedance
  • Open drain
  • Input
  • Tristate
  • Weak pull up or pull down

The PAD mode of operation is determined by DR_EN, OD_EN, REN and PU control signal. When push pull mode is selected, the source/sink impedance can be programmed to 50, 33, 66, 100 or 40 Ohms. DR_TY control bits are used to select the desired source/sink impedance. The source/sink impedance variation with PVT exceeds 25 % of its nominal value, trimming bits are provided to greatly reduce the variation. RTRIM bits are used for this purpose. ARASAN CAL I/O can be used to automatically reduce the variation to less than 8%.

Diagram


Sign Up For our Newsletter
© 2016 Arasan Chip Systems Inc. All Rights Reserved.