The Arasan 10/100 Ethernet Media Access Controller (MAC) IP core is compliant with the Ethernet IEEE 802.3-2002 standard and has passed interoperability testing at UNH-IOL. The 10/100 Ethernet IP core provides an 10/100 Mbps Media Independent Interface (MII) and an optional processor interface; it also supports Reduced MII (RMII) and Serial MII (SMII). The 10/100 Ethernet MAC IP is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers, and Ethernet adapter cards. The 10/100 Ethernet IP supports half-duplex mode at 10/100 Mbps and full-duplex mode at 10/100 Mbps.
The IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. An available 32-bit scatter-gather DMA transfer packet between the internal FIFOs and the host memory to enhance system performance. The IP core supports 4-bit MII based 10/100 Mbps PHY. IA MDIO/MDC (Management Data Input/Output and Management Data Clock) management interface provides controlling and management functions to external PHY devices.
The 10/100 Ethernet MAC IP provides enhanced programmable features for minimizing applications complexity and pre/post message processing. These features support MIB, SNMP, RMON, VLAN Q-Tag frame, and Jumbo frames. It also includes dynamic generation, checking, and stripping of FCS field, automatic pad field insertion, automatic re-transmission and detection of collision frames, collision avoidance and handling. Other features are generation and decoding of PAUSE control frames, frame boundary delimitation, frame synchronization, and error detection.
