CSI-2 Transmit

Arasan MIPI CSI-2 Transmitter v1.3 IP Core

 

The MIPI Camera Serial Interface (CSI-2) Transmitter, typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link to a CSI-2 Receiver in the application processor.

Arasan provides two MIPI CSI-2 Transmitter Controllers: CSI-2 v1.2 for D-PHY physical interface only, and CSI-2 v1.3 for the new MIPI C-PHY v1.0 and D-PHY v.1.1, v1.2, and a future v2.0. Arasan offers the C-PHY in a combination configuration that supports both C-PHY interfaces and D-PHY interfaces. Our implementation makes efficient use of the high frequency signally pins for a minimal overhead to support both physical interfaces.

The Arasan MIPI CSI-2 v1.3 Transmitter IP communicates over a D-PHY (or) C-PHY serial link to image processing block, part of the application engine. The Arasan CSI-2 Receiver IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.

Compliant with the following MIPI specifications

  • mipi_CSI-2_specification_v1-3
  • mipi_CSI-2_specification_v1-2
  • mipi_D-PHY_specification_v1-2
  • mipi_C-PHY_specification_v1-0

Pixel Data received from over the Camera Sensor Bus is packed into bytes by the Transmitter IP. The packing of the pixel into bytes follows the CSI-2 spec and based on the pixel format support. This IP calculates and appends an ECC/CRC value to a short packet (or) to the header of a long packet. Selection of ECC/CRC to the header is done based on the PHY connected. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends to the packet as a Packet Footer (PF). The packet is buffered in a FIFO and sent to one or more D-PHY/C-PHY depending on the lane distribution scheme set by the camera sensor/user.

Diagram

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