The Arasan MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.
Features
Compliant with the following MIPI specifications
Display Serial Interface (DSI-2) version 1.0
Display Pixel Interface (DPI-2) version 2.00
Display Bus Interface (DBI) version 2.00
Display Command Set (DCS) version 1.3
D-PHY version 1.2
D-PHY 2.0 and CPHY 1.1 (Combo PHY)
Deliverables
Verilog HDL of the IP Core
Synthesis scripts
Verification environment
User guides for design and verification
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
VIDEO Demo - Arasan CPHY/DPHY Combo Compliance Tester
