DSI Transmit

DSI v1.3 Transmit IP Core

The Next Generation of CSI, DSI and D-PHY: A webinar recorded July 9, 2014

The Arasan DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high speed serial connectivity for the host (mobile application processor) using 1 to 4 D-PHYs depending on bandwidth needs. Serial connectivity to the display module’s DSI device is implemented using 1 to 4 D-PHY’s (also available from Arasan), depending on display bandwidth needs. This IP connects to the D-PHYs through the PPI interface.

On the application processor side, Arasan’s DSI Host Controller provides the choice of DPI or DBI Interface to a graphics controller. A DBI interface provides downstream support of Types 1 to 3 display modules, and the DPI Interface is needed for Types 2 to 4 displays.

Initial configuration of Arasan’s MIPI DSI Host Controller can be done through programmed IO over the AHB bus, however, other bus interfaces can be provided upon request.


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