HSI Controller

HSI Controller IP Core

The High Speed Synchronous Serial Interface (HSI) Controller is used to provide high bandwidth, point-to-point, serial communication between two peers, like the cellular modem and application processor on a mobile platform, such as a smartphone or a tablet. The Arasan HSI Controller IP is designed to provide MIPI HSI 1.00 compliant connectivity to a SoC.

Three variations of the IP are currently available with support for AHB, AXI or OCP system buses. The HSI Controller’s internal registers are accessible through programmed IO transactions, in which case the IP functions as a bus slave. All data transfers between the SoC’s system memory and HSI interface happen either in PIO mode or in DMA mode as programmed by the driver/firmware.

All data received from system memory is held in the transmit FIFO and output as serial data over the HSI physical interface. Conversely, all serial data received from the HSI interface is captured in the receive FIFO before it is sent to the system memory. The FIFO’s and their associated logic can be structured with up to 8 logical channels, each with configurable depth.

Diagram


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