I3C Master

I3C Master Controller


The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.

The main purpose of MIPI I3C is threefold:

  • to standardize sensor communication
  • reduce the number of physical pins used in sensor system integration and
  • support low-power, high-speed and other critical features that are currently covered by I2C and SPI.



  • Compliant with MIPI I3C Specification V1.0
  • Supports up to 12.5 MHz operation using Push-Pull.
  • Open-Drain and Push-pull type transactions (as required)
  • Supports legacy I2C devices.
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C devices
  • Legacy I2C Messaging
  • I2C-like Single Data Rate Messaging (SDR)
  • Optional High Data Rate Messaging Modes (HDR)
  • Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present).
  • Reception of In-band Interrupt Support from the I3C Slave devices
  • Reception of Hot-Join from newly added I3C Slave devices.
  • Synchronous Timing Support and Asynchronous Time Stamping.
  • APB/AHB Target Interface for Configuring/Controlling the IP with Interrupt output.
  • Small 16-byte (Configurable) FIFO for transferring data between Master and the Slave devices.
  • Independent Clocks for AHB and the I3C Interface.
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