LLI Controller

MIPI LLI Controller

The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory. This is achieved by the low latency from the “companion” chip to the memory interface of the host chip.

The Low Latency Interface (LLI) is a point-to point-interconnect that allows two devices on the separate chips to communicate as if a device attached to or present on the remote chip is resident on the local chip. The connectivity to the remote chip’s devices is through standard interconnects (AHB/AXI/OCP), using memory mapped transactions.

LLI is expressed as a layered transaction level protocol, where the Initiator and Target devices on two linked chips exchange transactions without software intervention. LLI supports two types of traffic classes, Low Latency and Best Effort. MIPI LLI primarily targets low-latency cache refill transactions using the Low Latency (LL) traffic class, and uses the Best Effort (BE) traffic class for accessing all other memory mapped remote devices. LLI also provides a special set of high priority transactions for transmitting sideband signals, like interrupts, between two chips connected with LLI link.

Arasan’s MIPI LLI Controller resides on each instance of a chip pair, and the two controllers communicate at a physical level through the M-PHY® and their associated differential signals. The LLI Controller IP requires Arasan’s LLI specific MIPI M-PHY Type I IP as the Physical Layer and supports 1, 2, 3, 4 or 6 Lanes. The LLI Controller/M-PHY pairs on each chip together form a Low Latency Interface (LLI) bridge between the system buses/interconnects of two companion chips. This core is designed to be configurable as either a system bus master or slave, or both, for the Low Latency (LL) and Best Effort (BE) traffic classes defined in the MIPI LLI specification.


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