SLIMbus Device

SLIMbus Device IP Core

The Arasan SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.

SLIMbus has a TDM channel allocation structure for control messages and data. When its Framer is active, the device drives the SLIMbus clock, creates the SLIMbus frames, and enables the other SLIMbus devices and the SLIMbus host to synchronize and share the available bandwidth.

SLIMbus Device IP Core contains a configurable generic device that transfers data to and from remote SLIMbus components and legacy interfaces, like I2S, I2C and SPI, or interface directly to audio DAC’s and ADC’s through the Generic FIFO Interface. One or more port pairs of the generic device can be used for each kind of peripheral interface, up to a maximum of 16.

At a system level, this IP operates under control of a SLIMbus host, whose active manager and associated software stack monitors the characteristics and status of the SLIMbus device, and configures its registers and access to the bus accordingly.

Diagram


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