ONFI 3.2 PHY

ONFI 3.2 PHY

The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips. ONFI seeks to standardize the low level interface. ONFI 3.2 is the standard for High-Speed NAND Flash interface. It has multiple modes of operation like SDR, NV-DDR and NV-DDR2 modes. Micron’s ClearNAND operation such as Queue page read and Program page pause, Program page resume, Program page delay are also supported.

ONFI 3.2 PHY extends the benefits of ONFI 3.x and 2.3 standards. It provides a high speed interface supporting transfer rates up to 400 MT/s. It also supports the EZ-NAND interface. Lots of performance enhancing features like Interleaving operations, Multi-plane operations is supported.

ONFI 3.2 PHY incorporates the full TX/RX logic for NV-DDR2/NV-DDR mode of operation and is backwards compatible to SDR mode of operation. ONFI 3.2 improves on version ONFI 3.0 with more robust power sequencing to protect NAND flash, more flexible timing to support NAND usage in different topologies, improved parameters for testing, and other enhancements.

Included in the OFNI 3.2 PHY is a set of high speed I/O pads compatible to ONFI 1.8v 266 Mhz NV-DDR2 and 3v 100 Mhz NV-DDR.

Diagram


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