Embedded MMC (eMMC)
Designed for embedded applications that require high performance, small form factor, and high storage capacity, eMMC provides the support for embedded mass storage memory on embedded host systems. The eMMC protocol simplifies the access to NAND flash memories (such as MLC) to the host by hiding the functional differences among suppliers. Compliant to the latest JEDEC eMMC specifications, Arasan’s eMMC IP supports power-on-booting without the upper-level software driver. The explicit sleep mode allows the host to instruct the controller to directly enter the sleep mode. The interface supports an interface voltage of either 1.8V or 3.3V.
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts, and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
Secure Digital (SD)
The Arasan SD/SDIO Host IP Core controls communication between the SDIO Devices / SD Memory cards and the system using any of the system buses such as AHB, APB, OCP or any custom buses. It is designed to support SD and SDIO applications in handheld and consumer electronic devices. The Arasan SD/SDIO Host IP Core is fully compliant with the latest standard SD Host Controller Specification including ADMA2 which removes restrictions to allow data of any location and any size to be transferred in a 32-bit or 64-bit system memory. The Arasan IP core also supports multiple cards, 1-bit SD, 4-bit SD, SPI, high-speed, ultra-high-speed transfer modes. In an application with an AMBA interface, the Arasan SD/SDIO Host IP Core communicates with the ARM processor at a clock speed of 300 MHz. The SD/SDIO Host controller provides a configurable FIFO to meet the requirements of customer applications. An optional CPRM functional block can be incorporated to perform the Cipher algorithm for encryption and decryption. The Arasan SD/SDIO Host IP Core has been widely used in different SDIO applications by major chip vendors.
The SD Host IP is an RTL design in Verilog that implements an SD host controller in an ASIC or FPGA. The core includes RTL code, test scripts, and a test environment for full simulation verifications. The Arasan SD Host IP Core has been widely used in different SD applications by major semiconductor vendors with proven silicon.
